1. Field of the Invention
The present invention relates to a flip chip in a leaded molded package, and more particularly, to a flip chip in a leaded molded package with two stacked dies.
2. Description of the Prior Art
Semiconductor devices are becoming smaller and smaller. Additionally, as the need for speed, power and capacity increases, such a reduction in size leads to a contradiction in that smaller devices often have smaller capabilities.
In order to create smaller devices but with increased capabilities, the prior art has attempted to stack dies on top of one another. However, the prior art currently uses wire bonding for its interconnect scheme, which leads to higher resistance and inductance and does not allow for as thin a package as desired. Additionally, using wire bond techniques does not allow for the drain regions of a power MOSFET die to be exposed.